FET FIXED BIAS CIRUIT

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It is also called Gate bias. The circuit diagram of the FET fixed bias configuration is shown in the figure. The configuration includes A.C. levels Vi and Vo and the coupling capacitors. The resistor ensures that Vi appears at the input to the FET amplifier for AC Analysis.



DC Analysis:
  • Capacitors are considered an open circuit.
  • Also, IG = 0 A  &  VRG = IGRG = 0 V. The zero-voltage drop across RG permits replacing RG with a short circuit.


Step 1:   To Find VGS Expression:
Applying KVL to the input circuit,

               VGG + VGS = 0
        ∴    VGS = - VGG                   ---------(1)

The above equations show a fixed value of VGS.

Step 2:   To Find IDQ  Expression: 
By Shockley's Equation: 

     
  ∴ 

Step 3:   To Find VDS  Expression:
Applying KVL to the output circuit,

            VDD - IDRD -VDS = 0

      ∴   VDS = VDD - IDRD            ---------(2) 


Disadvantages:
  •  It requires two power supplies.

                            

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