FET SELF BIAS CIRCUIT

The circuit diagram of the self-bias configuration for N-channel JFET and P-channel JFET is shown in the figure. To operate a JFET, the gate-source junction should always be connected in a reverse-bias condition. To get this connection, negative VGS is required for N-channel JFET, and positive VGS is required for P-channel JFET. This can be achieved using the self-bias configuration shown in the diagram below.

DC Analysis:

Here we are considering an N-channel Self-Biased JFET configuration. For D.C analysis, coupling capacitors are replaced by open circuits, and also RG is replaced by short circuit. The equivalent circuit diagram is shown in below figure.

Step 1:   To Find VGS Expression:

The voltage drop across register RS is given as :

                    VS = IDRS

Now, the gate source voltage can be given as 

                    VGS = VG - VS

However, as the gate is connected to the ground, we can say that VG = 0 V. 

                   ∴  VGS = - VS         

                   ∴  VGS = - IDRS   ------------(1)

Step 2:   To Find IDQ  Expression: 

                

Substituting the value of VGS from equation (1) in the above equation, we get:

            

            

                 

Step 3:   To Find VDS  Expression:

Applying KVL to the output circuit, we get:

              VDD - IDRD   - VDS  - IDRS = 0

         ∴  VDS  = VDD - IDRD  - IDRS

              ∴     VDS  = VDD - ID (RD  + RS)   ------------- (2)