FET VOLTAGE DIVIDER BIAS CIRCUIT

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N-channel JFET with voltage divider bias is shown in the figure. In order to keep gate source voltage in reverse bias, the voltage at source is kept more positive compared to the voltage at gate terminal of JFET.

The source voltage is, VS = IDRS. The gate voltage is set by resistors R1 and R2.





DC Analysis: 
For DC analysis, coupling capacitors C1 and C2, and source resistor bypass capacitor CS are replaced by open circuits. The equivalent circuit diagram is shown in below figure.


Step 1: To Find VG Expression:

         

Step 2: To Find VGS Expression:

Applying KVL to the input circuit, 
                    VG - VGS - IDRS = 0
              ∴    VGS = VG - IDRS ------------- (1)

Step 3: To Find IDQ  Expression: 

By Shockley's Equation:

          

Step 4: To Find VDS  Expression:

Applying KVL to the output circuit,

            VDD - IDRD - VDS - IDRS = 0
   ∴       VDS = VDD - IDRD + IDRS
     ∴              VDS = VDD - ID (RD + RS ) ---------(2)

 Q-point Equation:


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